This application claims the priority of Korean Patent Application No. 2003-35603, filed on Jun. 3, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Technical Field
The present disclosure relates to a semiconductor device having a measuring pattern and a method of measuring the semiconductor device by using the measuring pattern.
2. Discussion of the Related Art
A known manufacturing process for a semiconductor integrated circuit forms a semiconductor integrated circuit having desired functions by depositing and etching conductive and insulated layers in a multi-layer form according to a design order. It is important to monitor the thickness of each layer that is layered in the manufacturing process so as to be able to forecast characteristics of a semiconductor device or to determine the ion injection energy in a subsequent ion injection process or an etching target.
A known method measures the thickness of insulated layers formed on a conductive wire pattern using an optical and capacitance measuring instrument. The thickness of the insulated layers can depend on the density of the wire pattern having the insulated layers thereon. In addition, if a width of the wire pattern is narrow, an exact measurement may be impossible due to the occurrence of a measuring error resulting from a narrow surface area of the wire pattern. Therefore, there is provided technology to reliably measure the thickness of the insulated layers formed on the wire pattern, even in an area of the wiring pattern having low density, by using correlations between electric resistance of a wire pattern and the thickness of the insulated layers.
A measuring area is set up inside a scribe area surrounding a chip area in which the semiconductor integrated circuit is formed, and an optical measurement of each layer in the circuit is performed in the scribe area during the circuit manufacturing process.
FIG. 1 is a schematic diagram illustrating a positional relationship between a chip and a measuring pattern area. Referring to FIG. 1, chip areas 10 in which the semiconductor integrated circuit is formed, are made on a semiconductor wafer, for instance, in a matrix in vertical and horizontal directions. A space between the chip areas 10 is called a scribe area 20. Each chip area 10 is separated into a unit chip along the scribe area 20. If the circuit manufacturing process is finished in each chip area 10, each unit chip is packaged in a subsequent packaging process.
A reference numeral 22 indicates a measuring pattern formed in a measuring area inside the scribe area 20. The measuring pattern 22 is formed in the same step as forming a circuit pattern of the semiconductor integrated circuit. Thus, an optical measurement on a material layer of the chip area 10 having the circuit pattern is performed on the measuring pattern 22 rather than on the circuit pattern of the chip area 10.
FIG. 2 is a schematic diagram illustrating a positional relationship of a conventional measuring pattern and a measuring beam area, and accordingly, provides an enlarged view of the measuring pattern 22 of FIG. 1.
Referring to FIG. 2, a beam area 24 indicating a reflection area of measuring beams originating from a measuring instrument is placed inside the measuring pattern 22. The measuring instrument can measure a thickness of a measured material layer by projecting light onto a target or the measured material layer. The measuring instrument may be, for example, a spectrometer or ellipsometer. A size of the beam area 24 projected onto the measured material layer from the measuring instrument is about 40 μm×40 μm. The size of the measuring pattern 22 is about 80 to approximately 100 μm×80 to approximately 100 μm.
FIG. 3 is a cross-section schematically illustrating the conventional measuring pattern of FIG. 2. Referring to FIG. 3, sections of the chip area 10 in which the semiconductor integrated circuit is formed, and a scribe area 20 surrounding the chip area 10, are illustrated as being adjacent. An integrated circuit pattern 26 and the measuring pattern 22 are respectively formed in a first material layer 30 made of one of an insulated or conductive material layer formed in a step of manufacturing a single crystal silicon substrate or of manufacturing the semiconductor integrated circuit in the chip area 10.
The integrated circuit pattern 26, formed as a trench shape with a certain interval in the chip area 10, is tightly clustered as a degree of integration of the semiconductor integrated circuit increases. However, the measuring pattern 22, made as a single trench shape inside the scribe area 20, is formed to be bigger than that of the beam area 24 in FIG. 2 in order to prevent a measuring error due to misalignment of the measuring instrument. The integrated circuit pattern 26 and the measuring pattern 22 can be simultaneously formed.
Thereafter, a second material layer 32 is deposited on the whole surface of the first material layer 30 in which the integrated circuit pattern 26 and the measuring pattern 22 are formed and in the trenches formed by the integrated circuit and measuring patterns 26 and 22. Then, a portion of the second material layer 32 is removed by a chemical mechanical polishing (CMP) process to expose the surface of the first material layer 30. Thus, the second material layer 32 remains inside the trench-shaped integrated circuit pattern 26 and the measuring pattern 22.
A difference occurs in a depositing or etching process for the semiconductor integrated circuit according to the density of a pattern formed on the substrate. In addition, the removal speed differs, particularly in the CMP process, according to the size of the pattern. For example, the thickness of the second material layer 32 formed in the integrated circuit pattern 26 (H1) differs from the thickness of the second material layer 32 formed in the measuring pattern 22 (H2). While almost no dishing occurs in the second material layer 32 that is formed in the integrated circuit pattern 26 having a high density, dishing occurs considerably in the second material layer 32 formed in the measuring pattern 22 having a relatively large size. That is, the difference occurs between H1, the actual thickness of the second material layer 32 in the chip area 10, and H2, the measured thickness of the second material layer 32 in the scribe area 20. Thereby, the reliability of measuring is decreased.
Therefore, the thickness of the second material layer 32 in the measuring pattern 22 is measured in order to measure the thickness of the second material layer 32 in the integrated circuit pattern 26 inside the chip area 10. In order to correct for the difference between H1 and H2 due to dishing, the actual thickness of the second material layer 32 formed in the integrated circuit pattern 26 is checked via a transmission electronic microscope (TEM) or a vertical scanning electronic microscope (VSEM). Then, using this actual thickness, a compensation value is estimated for the second material layer 32 formed in the measuring pattern 22.
However, the second material layer 32 formed in the measuring pattern 22 that is wider than that formed in the integrated circuit pattern 26 may have a different thickness according to a wafer in different lots or even in the same lot. Thus, it is difficult to arrive at an adequate compensation value for the whole lot by relying on photos displaying a limited number of points taken by the TEM or VSEM.
Moreover, loss of wafer, human and material resources results from the use of the TEM or VSEM. In addition, considerable time is required to take the photos with the TEM or VSEM. Accordingly, substantial time is taken in obtaining and applying an adequate compensation value in a subsequent process.